Role Description
We are seeking an AMS Verification Engineer with strong SerDes expertise to verify high-speed analog and mixed-signal interfaces. This role focuses on validating the functionality, performance, and robustness of SerDes IP and SoC integrations across PVT corners. The ideal candidate will work closely with analog designers, digital architects, and system teams to ensure first-silicon success for multi-Gbps links.

Key Responsibilities

• Develop comprehensive verification plans for SerDes architectures (TX, RX, PLL/CDR, equalization, and calibration loops)

• Build and maintain mixed-signal testbenches using Verilog-AMS, SystemVerilog, and real-number models (RNM)

• Verify analog/digital interactions including clocking, reset, power-up, and calibration sequences

• Perform functional and performance verification of high-speed links (jitter, BER, eye diagrams, latency)

• Validate PLLs, CDRs, serializers/deserializers, and adaptive equalization algorithms

• Run AMS simulations across PVT corners, Monte Carlo, and stress conditions

• Analyze simulation results, debug failures, and collaborate with design teams to resolve issues

• Support top-level SerDes integration and system-level verification

• Develop automation, scripts, and reusable verification components

• Provide verification sign-off support for tape-out

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field

• Strong understanding of SerDes architectures and high-speed signaling fundamentals

• Solid knowledge of analog and mixed-signal circuits (PLL, CDR, amplifiers, comparators)

• Proficiency in Verilog-AMS and/or SystemVerilog

• Experience with AMS simulators (Spectre AMS, Xcelium AMS, VCS AMS, or equivalent)

• Experience measuring and analyzing jitter, eye diagrams, and BER

• Ability to debug complex cross-domain (analog/digital) issues

• Scripting experience (Python, Tcl, Perl, or similar)

Preferred Qualifications

• Experience with multi-Gbps standards (PCIe, Ethernet, USB, SATA, DisplayPort, or proprietary links)

• Knowledge of real-number modeling (RNM) and behavioral modeling for SerDes blocks

• Familiarity with UVM-based digital verification environments

• Understanding of equalization techniques (FFE, DFE, CTLE)

• Experience with low-power and power-aware verification

• Prior tape-out experience in advanced technology nodes