Role description

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We are seeking a skilled and detail-oriented Analog Layout Engineer to join our high-speed SerDes design team. In this role, you will be responsible for the full-custom layout of critical analog and mixed-signal blocks used in next-generation Serializer/Deserializer (SerDes) IP. The ideal candidate will have strong layout expertise in high-speed analog circuits and a solid understanding of layout techniques required to meet stringent performance, area, and reliability goals.

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Key Responsibilities:
 

• Create full-custom layout of analog and mixed-signal blocks including TX drivers, RX front-ends, PLLs, CDRs, bias circuits, and equalizers.

• Work closely with circuit designers to understand layout-sensitive requirements including matching, symmetry, shielding, and critical routing paths.

• Perform floorplanning, device placement, routing, and hierarchical block integration.

• Execute physical verification flows including DRC, LVS, ERC, and EMIR using industry-standard tools.

• Extract parasitics (PEX) and assist in layout- and parasitic-aware simulations.

• Optimize layout for performance, area, and manufacturability across process corners and voltage/temperature variations.

• Follow design and layout guidelines to ensure consistency and high quality across blocks.

• Collaborate with cross-functional teams including digital, packaging, and test to support full-chip integration and bring-up.